Photo of Im, Jang-Hi

Jang-Hi Im

Research Professor

Email: jayim@mail.utexas.edu
Phone: (512) 471-9858
Office: MER 2.206G

Dr. Jang-hi ('Jay') Im is a Research Professor at The University of Texas at Austin, in the Laboratory for Interconnect & Packaging, where he has been since 2005.  Prior to 2004, he had been with The Dow Chemical Company for 28 years, taking on various R&D positions including Research Scientist in microelectronics, where he headed the materials science and adhesion efforts for BCB and SiLK dielectric polymers.  His current research areas at the University are in semiconductor packaging and reliability, 3D integration with through-silicon-vias (TSVs), electromigration of Pb-free solders, materials science of dielectric films, and metrology for thin film testing. He received his B.S. degree in mechanical engineering from Seoul National University, Korea, and both M.S. degree in mechanical engineering and doctoral (Sc.D) degree in materials science & engineering from Massachusetts Institute of Technology.  He has nine U.S. patents and over 120 published papers.  He is a Senior Member of IEEE.

Most Recent Publications

  1. T. Jiang, S-K Ryu, Q. Zhao, J. Im, H-Y Son, K-Y Byun, R. Huang, and P. S. Ho, "Measurement and Analysis of Thermal Stresses in 3-D Integrated Structures Containing Through-Silicon-Vias," IITC Proc., (June 2012), pp. paper 3-2
  2. Xuefeng Zhang, Yiwei Wang, Jay Im, and Paul S. Ho, "Chip-Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-k Interconnects in Flip-Chip Packages", Vol. 12, (2012), 2, pp. 462-469
  3. S-K Ryu, R. Huang, T. Jiang, J. Im, P. S. Ho, H-y Son, and K-y Byun, "Characterization of Thermal Stresses in Through-Silicon Vias for 3D Interconnects by Bending Beam Technique," Appl. Phys. Lett. , Vol. 100, (2012), pp. 041901-1-04190-4
  4. S-K Ryu, Q. Zhao, M. Hecker, H-Y Son, K-Y Byun, J. Im, P. S. Ho, and R. Huang, "Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects," J. Appl. Phys., Vol. 111, (2012), 6, pp. 0635131-0635138
  5. S-K Ryu, K-H Lu, T. Jiang, J. Im, R. Huang, and P. S. Ho, "Effect of Thermal Stresses on Carrier Mobility and Keep-out Zone around Through-Silicon Vias for 3-D Integration," IEEE Trans. On Device And Materials Reliability (TDMR), Vol. 12, (2012), 2, pp. 255-262
  6. Y. Wang, K. H. Lu, V. Gupta, L. Stiborek, D. Shirley, S-H Chae, J. Im, and P. S. Ho, "Effects of Sn Grain Structure on the Electromigration of Sn-Ag Solder Joints," J. Mat. Res., Vol. 27, (2011), 8, pp. 1131-1141
  7. S-K Ryu, K-H Lu, X. Zhang, J. Im, P. S. Ho, and R. Huang, "Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon-Vias for 3-D Interconnects," IEEE Trans. Device & Mater. Reliability, Vol. 11, (2011), pp. 35-43
  8. D. K. Shin, Y. H. Song, and J. Im, "Effect of PCB Surface Modifications on the EMC-to-PCB Adhesion in Electronic Packages," IEEE Tr. Components And Packaging Technologies, Vol. 33, (June 2010), 2, pp. 498-508
  9. Suk-Kyu Ryu, Kuan-Hsun Lu, Xuefeng Zhang, Jay Im, Paul S. Ho, and Rui Huang, "Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon-Vias for 3-D Interconnects," IEEE Tr. Device & Materials Reliability, (2010)
  10. Bin Li, Qiu Zhao, Huai Huang, Zhiquan Luo, Min K. Kang, Jay Im, Richard Allen, Michael Cresswell, Rui Huang, and Paul S. Ho, "Indentation of single-crystal silicon nanolines: Buckling and contact friction at nanoscales ," J.Appl. Phys., Vol. 105, (2009), pp. 073510
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