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4. Batch-Fabricated Nanowire Plasmonic Probes for Near Field Imaging of Single Molecules and Cells
Graduate Student Researcher:
Post-doctoral Researcher: Dr. Yong Lee
Sponsor: Texas Higher Education Coordinating Board Norman Hackerman Advanced Research Program
Project Status: Current
3. Room-Temperature Scanning Single-Electron-Transistor Microscopy of Nanoelectronic Devices
Gradate Student Researcher: Michael T. Pettes
Post-doctoral Researcher: Dr. Yong Lee
Collaboration: Prof. Zhen Yao, UT Austin
Sponsor: Texas Higher Education Coordinating Board Norman Hackerman Advanced Research Program
Project Status: Current
Silicon-based microelectronics has experienced phenomenal growth according to Moore's law. One of the main driving forces behind this growth has been the excellent scaling property of metal-oxide-semiconductor field−effect transistors. Currently the channel length in these devices is already in the sub-100 nm regime. As the devices continue to shrink in size, one can expect that very soon only a few electrons can control a device's performance. Thus it is imperative to develop a characterization tool capable of detecting the electrons and charged dopant atoms in the devices with single electron charge sensitivity and nanometer spatial resolution. Similar needs also exist for non-conventional devices based on, for example, molecules, carbon nanotubes, and semiconductor nanowires. In the past, several techniques based on scanning probe microscopy have proven useful in the characterization of electronic devices. However, they are generally unable to resolve individual electron charges and are limited to spatial resolution of a few tens of nanometer.
The overall objective of this project is to develop room-temperature scanning single-electron-transistor microscopy (SSETM) with unprecedented charge sensitivity and spatial resolution and to employ the technique to characterize nanoelectronic devices. Central to the SSETM is a scanning probe with a built-in single-electron transistor (SET), which consists of a small conducting island weakly coupled to the source and drain electrodes. If the island is made small enough such that the electrostatic charging energy for adding one electron is larger than the thermal energy, electrons can only tunnel on and off the island one by one. In this regime, even tiny charge or potential fluctuations near the central island while the sensor is being scanned over the sample surface can induce a large change in the current through the device. The charge sensitivity of the SSETM is estimated to be ~1% of an electron charge, which is at least two orders of magnitude greater than other scanning probe-based techniques. The technique is also noninvasive because of its high sensitivity. Furthermore, it possesses very high spatial resolution since the response of the SET is mainly determined by the size of the island which can be made extremely small. Despite the advantages of the SSETM, only one group so far succeeded in implementing the SSETM and its operation was limited to very low temperatures, which is not suitable for studying practical electronic devices. Our proposed research is made feasible by a recent breakthrough in developing a process to reliably fabricate room-temperature SETs based on molecular self-assembly between two nanometer-spaced gold electrodes. This SET structure will be integrated at the apex of sharp tips for atomic force microscopy. We will employ the technique to investigate a variety of electronic properties including doping, band bending, and work function in silicon, III−V, and carbon nanotube devices. If successful, we believe that the room−temperature SSETM technique to be developed has a potential to become an invaluable tool with unprecedented capability for the characterization of nanoelelectronic devices. The highly interdisciplinary nature of this research will also result in broad training of students.
2. Nanoscale Interconnect Structures for Future Microelectronics
Gradate Student Researchers: Bin Li, Anastassios Mavrokefalos
Post-doctoral Fellow: Dr. Yunyu Wang
Collaboration: Prof. Paul S. Ho, Prof. Zhen Yao, UT Austin
Sponsor: SEMATECH through Advanced Materials Research Center
Project Status: Completed
This research aims to develop nanofabrication methods to fabricate 10-50 nm wide metal nanowire arrays to examine material limits for interconnects
1. Investigation of Electrical Conductivity of Silicide and Copper Nanowires
Gradate Student Researcher: Bin Li
Collaboration: Prof. Paul S. Ho, UT Austin
Sponsor: National Institute of Standards and Technology
Project Status: Completed